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adc1002s020 single 10 bits adc, up to 20 mhz rev. 03 ? 2 july 2012 product data sheet 1. general description the adc1002s020 is a 10-bit high-speed analog-to-digital converter (adc) for professional video and other applications. it converts with 3.0 v to 5.25 v operation the analog input signal into 10-bit binary-coded digital words at a maximum sampling rate of 20 mhz. all digital inputs and outputs are cmos compatible. a standby mode allows a reduction of the device power consumption to 4 mw. 2. features ? 10-bit resolution ? 3 .0 v to 5.25 v operation ? sa mpling rate up to 20 mhz ? dc sampling allowed ? high signal-to-noise ratio over a large analog input frequency range (9.3 effective bits at 1.0 mhz; full-scale input at f clk = 20 mhz) ? in-r ange (ir) cmos output ? cmos/t ransistor-transistor logic (ttl) compatible digital inputs and outputs ? exte rnal reference voltage regulator ? power dissip ation only 53 mw (typical value) ? l ow analog input capacitance, no buffer amplifier required ? s tandby mode ? no samp le-and-hold circuit required 3. applications ? video data digitizing ? came ra ? camcorder ? rad io communication ? bar code scanner
adc1002s020_3 ? idt 2012. all rights reserved. product data sheet rev. 03 ? 2 july 2012 2 of 18 integrated device technology adc1002s020 single 10 bits adc, up to 20 mhz 4. quick reference data table 1. quick reference data v dda = v7 to v9 = 3.3 v; v ddd = v4 to v3 = v18 to v19 = 3.3 v; v ddo = v20 to v21 = 3.3 v; v ssa , v ssd and v sso shorted together; v i(p-p) = 1.83 v; c l = 20 pf; t amb = 0 ? c to 70 ? c; typical values measured at t amb = 25 ? c unless otherwise specified. symbol parameter conditions min typ max unit v dda analog supply voltage 3.0 3.3 5.25 v v ddd1 digital supply voltage 1 3.0 3.3 5.25 v v ddd2 digital supply voltage 2 3.0 3.3 5.25 v v ddo output supply voltage 3.0 3.3 5.25 v i dda analog supply current - 7.5 10 ma i ddd digital supply current - 7.5 10 ma i ddo output supply current f clk = 20 mhz; ramp input; c l = 20 pf - 1 2 ma inl integral non-linearity ramp input; see figu re 6 - ? 1 ? 2 lsb dnl differential non-linearity ramp input; see figu re 7 - ? 0. 25 ? 0.7 lsb f clk(max) maximum clock frequency 20 - - mhz p tot total power dissipation operating; v ddd = 3.3 v - 53 73 mw standby mode - 4 - mw 5. ordering information table 2. ordering information type number package name description version ADC1002S020HL lqfp32 plastic low profile quad flat package; 32 leads; body 5 ? 5 ? 1.4 mm sot401-1
adc1002s020_3 ? idt 2012. all rights reserved. product data sheet rev. 03 ? 2 july 2012 3 of 18 integrated device technology adc1002s020 single 10 bits adc, up to 20 mhz 6. block diagram 19 v ssd2 10 14 r lad 11 15 rb rm rt vi 18 v ddd2 7 2 v dda 28 29 30 31 27 d4 d5 d6 d7 d8 26 25 1 6 d3 d2 23 d1 22 d0 d9 in - range latch cmos outputs latches clock driver 014aaa482 5 clk 16 oe stdby adc1002s020 20 v ddo 9 v ssa analog ground digital ground 2 digital ground 1 3 v ssd1 21 v sso output ground analog voltage input data outputs lsb msb 4 v ddd1 ir output analog - to - digital converter cmos output fig 1. block diagram
adc1002s020_3 ? idt 2012. all rights reserved. product data sheet rev. 03 ? 2 july 2012 4 of 18 integrated device technology adc1002s020 single 10 bits adc, up to 20 mhz 7. pinning information 7.1 pinning ADC1002S020HL 014aaa483 d9 1 ir 2 v ssd1 3 v ddd1 4 clk 5 stdby 6 v dda 7 n.c. 8 n.c. 24 d1 23 d0 22 v sso 21 v ddo 20 v ssd2 19 v ddd2 18 n.c. 17 v ssa 9 rb 10 rm 11 n.c. 12 n.c. 13 vi 14 rt 15 oe 16 n.c. 32 d8 31 d7 30 d6 29 d5 28 d4 27 d3 26 d2 25 fig 2. pin configuration 7.2 pin description table 3. pin description symbol pin description d9 1 data output; bit 9 (most significant bit (msb)) ir 2 in-range data output v ssd1 3 digital ground 1 v ddd1 4 digital supply voltage 1 (3.0 v to 5.25 v) clk 5 clock input stdby 6 standby mode input v dda 7 analog supply voltage (3.0 v to 5.25 v) n.c. 8 not connected v ssa 9 analog ground rb 10 reference voltage bottom input rm 11 reference voltage middle input n.c. 12 not connected n.c. 13 not connected vi 14 analog voltage input rt 15 reference voltage top input oe 16 output enable input (active low) n.c. 17 not connected v ddd2 18 digital supply voltage 2 (3.0 v to 5.25 v)
adc1002s020_3 ? idt 2012. all rights reserved. product data sheet rev. 03 ? 2 july 2012 5 of 18 integrated device technology adc1002s020 single 10 bits adc, up to 20 mhz 8. limiting values table 4. limiting values in accordance with the absolute maximum rating system (iec 60134). symbol parameter conditions min max unit v dda analog supply voltage [1] ? 0.3 +7.0 v v ddd digital supply voltage [1] ? 0.3 +7.0 v v ddo output supply voltage [1] ? 0.3 +7.0 v ? v dd supply voltage difference v dda ? v ddd v ddd ? v ddo v dda ? v ddo ? 0.1 +4.0 v v i input voltage referenced to v ssa ? 0.3 +7.0 v v i(a)(p-p) peak-to-peak analog input voltage referenced to v ssd - v ddd v i o output current - 10 ma t stg storage temperature ? 55 +150 ?c t amb ambient temperature ? 20 +75 ?c t j junction temperature - 150 ?c [1] the supply voltages v dda , v ddd and v ddo may have any value between ? 0.3 v and +7.0 v provided that the supply voltage ? v dd remains as indicated. 9. thermal characteristics table 5. thermal characteristics symbol parameter condition value unit r th(j-a) thermal resistance from junction to ambient in free air 90 k/w v ssd2 19 digital ground 2 v ddo 20 positive supply voltage for output stage (3.0 v to 5.25 v) v sso 21 output stage ground d0 22 data output; bit 0 (least significant bit (lsb)) d1 23 data output; bit 1 n.c. 24 not connected d2 25 data output; bit 2 d3 26 data output; bit 3 d4 27 data output; bit 4 d5 28 data output; bit 5 d6 29 data output; bit 6 d7 30 data output; bit 7 d8 31 data output; bit 8 n.c. 32 not connected table 3. pin description ?continued symbol pin description
adc1002s020_3 ? idt 2012. all rights reserved. product data sheet rev. 03 ? 2 july 2012 6 of 18 integrated device technology adc1002s020 single 10 bits adc, up to 20 mhz 10. characteristics table 6. characteristics v dda = v7 to v9 = 3.3 v; v ddd = v4 to v3 = v18 to v19 = 3.3 v; v ddo = v20 to v21 = 3.3 v; v ssa , v ssd and v sso shorted together; v i(p-p) = 1.83 v; c l = 20 pf; t amb = 0 q c to 70 q c; typical values measured at t amb = 25 q c unless otherwise specified. symbol parameter conditions min typ max unit supplies v dda analog supply voltage 3.0 3.3 5.25 v v ddd1 digital supply voltage 1 3.0 3.3 5.25 v v ddd2 digital supply voltage 2 3.0 3.3 5.25 v v ddo output supply voltage 3.0 3.3 5.25 v ' v dd supply voltage difference v dda v ddd; v ddd v ddo ; v dda v ddo 0.2 - +0.2 v i dda analog supply current - 7.5 10 ma i ddd digital supply current - 7.5 10 ma i ddo output supply current f clk = 20 mhz; ramp input; c l = 20 pf - 1 2 ma p tot total power dissipation operating; v ddd = 3.3 v - 53 73 mw standby mode - 4 - mw inputs clock input clk (referenced to v ssd ); [1] v il low-level input voltage 0 - 0.3 v ddd v v ih high-level input voltage v ddd d 3.6 v 0.6 v ddd - v ddd v v ddd > 3.6 v 0.7 v ddd - v ddd v i il low-level input current v clk = 0.3 v ddd 1 0 +1 p a i ih high-level input current v clk = 0.7 v ddd - - 5 p a z i input impedance f clk = 20 mhz - 4 - k : c i input capacitance f clk = 20 mhz - 3 - pf inputs oe and stdby (referenced to v ssd ); see table 7 and 8 v il low-level input voltage 0 - 0.3 v ddd v v ih high-level input voltage v ddd d 3.6 v 0.6 v ddd - v ddd v v ddd > 3.6 v 0.7 v ddd - v ddd v i il low-level input current v il = 0.3 v ddd 1 - - p a i ih high-level input current v ih = 0.7 v ddd - - 1 p a analog input vi (referenced to v ssa ) i il low-level input current v i = v rb - 0 - p a i ih high-level input current v i = v rt - 35 - p a z i input impedance f i = 1 mhz - 5 - k : c i input capacitance f i = 1 mhz - 8 - pf reference voltages for the resistor ladder; see table 8 v rb voltage on pin rb 1.1 1.2 - v v rt voltage on pin rt 3.0 3.3 v dda v
adc1002s020_3 ? idt 2012. all rights reserved. product data sheet rev. 03 ? 2 july 2012 7 of 18 integrated device technology adc1002s020 single 10 bits adc, up to 20 mhz v ref(dif) differential reference voltage v rt v rb 1.9 2.1 3.0 v i ref reference current - 7.2 - ma r lad ladder resistance - 290 - : tc rlad ladder resistor temperature coefficient - 539 - m : /k - 1860 - ppm v offset offset voltage bottom [2] - 135 - mv top [2] - 135 - mv v i(p-p) peak-to-peak input voltage [3] 1.66 1.83 2.35 v digital outputs d9 to d0 and ir (referenced to v ssd ) v ol low-level output voltage i o = 1 ma 0 - 0.5 v v oh high-level output voltage i o = 1 ma v ddo 0.5 - v cco v i oz off-state output current 0.5 v < v o < v ddo 20 - +20 p a switching characteristics; clock input clk; see figure 4 [1] f clk(max) maximum clock frequency 20 - - mhz t w(clk)h high clock pulse width 15 - - ns t w(clk)l low clock pulse width 15 - - ns analog signal processing (f clk = 20 mhz) linearity inl integral non-linearity ramp input; see figure 6 - r 1 r 2 lsb dnl differential non-linearity ramp input; see figure 7 - r 0.25 r 0.7 lsb input set response; see figure 8 [4] t s(lh) low to high settling time full-scale square wave - 4 6 ns t s(hl) high to low settling time full-scale square wave - 4 6 ns harmonics; see figure 9 [5] thd total harmonic distortion f i = 1 mhz - 63 - db signal-to-noise ratio; see figure 9 [5] s/n signal-to-noise ratio without harmonics; f i = 1 mhz - 60 - db effective bits; see figure 9 [5] enob effective number of bits f i = 300 khz - 9.5 - bits f i = 1 mhz - 9.3 bits f i = 3.58 mhz - 8.0 bits table 6. characteristics ?continued v dda = v7 to v9 = 3.3 v; v ddd = v4 to v3 = v18 to v19 = 3.3 v; v ddo = v20 to v21 = 3.3 v; v ssa , v ssd and v sso shorted together; v i(p-p) = 1.83 v; c l = 20 pf; t amb = 0 q c to 70 q c; typical values measured at t amb = 25 q c unless otherwise specified. symbol parameter conditions min typ max unit
adc1002s020_3 ? idt 2012. all rights reserved. product data sheet rev. 03 ? 2 july 2012 8 of 18 integrated device technology adc1002s020 single 10 bits adc, up to 20 mhz [1] in addition to a good layout of the digital and analog ground, it is recommended that the rise and fall times of the clock must not be less than 1 ns. [2] analog input voltages producing code 0 up to and including code 1023: a) v offset bottom is the difference between the analog input which produces data equal to 00 and the reference voltage on pin rb (v rb ) at t amb = 25 ? c. b) v offset top is the difference between the reference voltage on pin rt (v rt ) and the analog input which produces data outputs equal to code 1023 at t amb = 25 ? c . [3] to ensure the optimum linearity performance of such a converte r architecture the lower and upper extremities of the converte r reference resistor ladder are connected to pins rb and rt via offset resistors r ob and r ot as shown in figure 3. a) the current flowing into the resistor ladder is i v rt v rb ? r ob r l r ot ++ --------------------------------------- = and the full-scale input range at the converter, to cover code 0 to 1023 is v i r l i l ? r l r ob r l r ot ++ --------------------------------------- v rt v rb + ?? ? 0.871 v rt v rb ? ?? ? == = b) since r l , r ob and r ot have similar behavior with respect to process and temperature variation, the ratio r l r ob r l r ot ++ --------------------------------------- will be kept reasonably constant from devic e to device. consequen tly variation of the output codes at a given input voltage dep ends mainly on the difference v rt ?? v rb and its variation with temperature and supply voltage. when several adcs are connected in parallel and fed with the same reference source, the matching between each of them is optimized. [4] the analog input settling time is the minimum time required for the input signal to be stabilized after a sharp full-scale i nput (square wave signal) in order to sample the signal and obtain correct output data. [5] effective bits are obtained via a fast fourier transform (f f t) treatment taking 8000 acquisition points per equivalent funda mental period. the calculation takes into acc ount all harmonics and noise up to half th e clock frequency (nyqui st frequency). conversi on to signal-to-noise and distortion (sinad) ratio: sinad = enob ? 6.02 + 1.76 db. [6] output data acquisition: the output data is available af ter the maximum delay time of t d(o) . timing (f clk = 20 mhz; c l = 20 pf); see figure4 [6] t d(s) sampling delay time - - 5 ns t h(o) output hold time 5 - - ns t d(o) output delay time v ddo = 4.75 v 8 12 15 ns v ddo = 3.15 v 8 17 20 ns 3-state output delay times; see figure 5 t dzh float to active high delay time - 14 18 ns t dzl float to active low delay time - 16 20 ns t dhz active high to float delay time - 16 20 ns t dlz active low to float delay time - 14 18 ns standby mode output delay times t tlh low to high transition time stand-by - - 200 ns t thl high to low transition time start-up - - 500 ns table 6. characteristics ?continued v dda = v7 to v9 = 3.3 v; v ddd = v4 to v3 = v18 to v19 = 3.3 v; v ddo = v20 to v21 = 3.3 v; v ssa , v ssd and v sso shorted together; v i(p-p) = 1.83 v; c l = 20 pf; t amb = 0 ? ? ? symbol parameter conditions min typ max unit
adc1002s020_3 ? idt 2012. all rights reserved. product data sheet rev. 03 ? 2 july 2012 9 of 18 integrated device technology adc1002s020 single 10 bits adc, up to 20 mhz 11. additional information relating to table 6 014aaa480 rt rb rm r lad r ot r l r l r l r l i l r ob code 1023 code 0 fig 3. converter reference resistor ladder table 7. mode selection oe d9 to d0 ir 1 high impedance high impedance 0 active; binary active table 8. standby selection stby d9 to d0 i cca + i ccd 1 last logic state 1.2 ma (typical value) 0 active 15 ma (typical value) table 9. output coding and input voltage (typical values; referenced to v ssa ) code v i(a)(p-p) (v) ir binary outputs d9 to d0 underflow < 1.335 0 00 0000 0000 0 1.335 1 00 0000 0000 1 - 1 00 0000 0001 ? - ? ? 1022 - 1 11 1111 1110 1023 3.165 1 11 1111 1111 overflow > 3.165 0 11 1111 1111
adc1002s020_3 ? idt 2012. all rights reserved. product data sheet rev. 03 ? 2 july 2012 10 of 18 integrated device technology adc1002s020 single 10 bits adc, up to 20 mhz sample n + 1 sample n clk 014aaa481 sample n + 2 sample n + 1 sample n sample n + 2 50% v i data d0 to d9 v ddo 0 v 50% data n + 1 data n data n ? 1 data n ? 2 t d(o) t w(clk)h t w(clk)l t d(s) t h(o) fig 4. timing diagram
adc1002s020_3 ? idt 2012. all rights reserved. product data sheet rev. 03 ? 2 july 2012 11 of 18 integrated device technology adc1002s020 single 10 bits adc, up to 20 mhz low high high low adc1002s020 v ddd v ddo s1 oe oe output data output data 10 % 50 % 50 % 90 % 50 % t dlz t dzl t dhz t dzh 20 pf 3.3 k s1 test v ddo t dlz v ddo t dzl v sso t dzh t dhz v sso 014aaa484 frequency on pin oe = 100 khz. fig 5. timing diagram and test condit ions of 3-state output delay time 014aaa491 ?0.2 0.2 0.6 a (lsb) ?0.6 f (mhz) 0 1200 800 400 200 1000 600 1023 fig 6. typical integral non-linearity (inl) performance
adc1002s020_3 ? idt 2012. all rights reserved. product data sheet rev. 03 ? 2 july 2012 12 of 18 integrated device technology adc1002s020 single 10 bits adc, up to 20 mhz 014aaa492 ?0.05 0.05 ?0.15 0.15 0.25 a (lsb) ?0.25 f (mhz) 0 1200 800 400 200 1000 600 1023 fig 7. typical differential non-linearity (dnl) performance 014aaa479 code 1023 code 0 50 % 50 % clk vi t s(lh) t s(hl) 50 % 50 % 5 ns 5 ns 2 ns 2 ns fig 8. analog input settling time diagram
adc1002s020_3 ? idt 2012. all rights reserved. product data sheet rev. 03 ? 2 july 2012 13 of 18 integrated device technology adc1002s020 single 10 bits adc, up to 20 mhz 014aaa493 ?80 ?40 0 a (db) ?120 f (mhz) 0 10 7.51 2.5 5.01 effective bits: 9.59; thd = ?76.60 db. harmonic levels (db): 2nd = ?81.8 5; 3rd = ? 87.56; 4th = ? 88.81; 5th = ? 88.96; 6th = ?79.58. fig 9. typical fast fourier transform (f clk = 20 mhz; f i = 1 mhz)
adc1002s020_3 ? idt 2012. all rights reserved. product data sheet rev. 03 ? 2 july 2012 14 of 18 integrated device technology adc1002s020 single 10 bits adc, up to 20 mhz 014aaa485 v ddo d9 to d0 ir v sso v dda vi v ssa 014aaa486 fig 10. d9 to d0 and ir outputs fig 11. vi analog input 014aaa487 v ddo v sso oe stdby v dda rt rm rb v ssa 014aaa488 r lad r lad r lad r lad fig 12. oe and stdby inputs fig 13. rb, rm and rt inputs v ddd clk 1 / 2 v ddd v ssd 014aaa489 fig 14. clk input
adc1002s020_3 ? idt 2012. all rights reserved. product data sheet rev. 03 ? 2 july 2012 15 of 18 integrated device technology adc1002s020 single 10 bits adc, up to 20 mhz 12. application information 12.1 application diagram adc1002s020 014aaa490 1 2 3 4 24 23 22 21 20 19 18 17 9 d9 ir v ssd1 v sso v ddo v ssd2 v ddd2 v ddd1 v dda clk stdby n.c. (2) v ssa v ssa v ssa v ssa rb (1) rt (1) oe vi (4) n.c. (2) n.c. (2) rm (1) (3) n.c. (2) n.c. (2) n.c. (2) d1 d0 5 6 7 8 10 11 12 13 14 15 16 32 31 100 nf 100 nf 100 nf 30 29 28 27 26 25 d5 d4 d3 d2 d8 d7 d6 the analog and digital supplies should be separated and decoupled. the external voltage reference generator must be built in such a way that a good supply voltage ripple rejection is achieved with respect to the lsb value. eventually, the reference ladder voltages can be derived from a well regulated v dda supply through a resistor bridge and a decoupling capacitor. (1) rb, rm and rt are decoupled to v ssa (2) pins 8, 12, 13, 17, 24 and 32 should be connected to the closest ground pin in order to prevent noise influence (3) when rm is not used, pin 11 can be left open ci rcuit , avoiding the decoup ling capacitor. in any case, pin 11 must not be grounded. (4) when the analog input signal is ac coupled, an input bias or a clamping level must be applied to vi input (pin 14). fig 15. application diagram
adc1002s020_3 ? idt 2012. all rights reserved. product data sheet rev. 03 ? 2 july 2012 16 of 18 integrated device technology adc1002s020 single 10 bits adc, up to 20 mhz 13. package outline 0.2 unit a max. a 1 a 2 a 3 b p ce (1) eh e ll p z ywv references outline version european projection issue date iec jedec jeita mm 1.6 0.15 0.05 1.5 1.3 0.25 0.27 0.17 0.18 0.12 5.1 4.9 0.5 7.15 6.85 1 0.95 0.55 7 0 o o 0.12 0.1 dimensions (mm are the original dimensions) note 1. plastic or metal protrusions of 0.25 mm maximum per side are not included. 0.75 0.45 sot401-1 136e01 ms-026 00-01-19 03-02-20 d (1) (1)(1) 5.1 4.9 h d 7.15 6.85 e z 0.95 0.55 d b p e e b 8 d h b p e h v m b d z d a z e e v m a x 1 32 25 24 17 16 9 a 1 a l p detail x l (a ) 3 a 2 y w m w m 0 2.5 5 mm scale lqfp32: plastic low profile quad flat package; 32 leads; body 5 x 5 x 1.4 mm sot401-1 c pin 1 index fig 16. package outline sot401-1 (lqfp32)
adc1002s020_3 ? idt 2012. all rights reserved. product data sheet rev. 03 ? 2 july 2012 17 of 18 integrated device technology adc1002s020 single 10 bits adc, up to 20 mhz 14. revision history table 10. revision history document id release date data sheet status change notice supersedes adc1002s020_3 20120702 product data sheet - adc1002s020_2 adc1002s020_2 20080813 product data sheet - adc1002s020_1 modifications: corrections made to cross references and note 3 a) in table ? 6. adc1002s020_1 20080612 product data sheet - - 15. contact information for more information or sales office addresses, please visit: http://www.idt.com
adc1002s020_3 ? idt 2012. all rights reserved. product data sheet rev. 03 ? 2 july 2012 18 of 18 integrated device technology adc1002s020 single 10 bits adc, up to 20 mhz 16. contents 1 general description . . . . . . . . . . . . . . . . . . . . . . 1 2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 4 quick reference data . . . . . . . . . . . . . . . . . . . . . 2 5 ordering information . . . . . . . . . . . . . . . . . . . . . 2 6 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 7 pinning information . . . . . . . . . . . . . . . . . . . . . . 4 7.1 pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 7.2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 8 limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5 9 thermal characteristics . . . . . . . . . . . . . . . . . . 5 10 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 6 11 additional informa tion relating to table 6 . . . 9 12 application information . . . . . . . . . . . . . . . . . 15 12.1 application diagram . . . . . . . . . . . . . . . . . . . . 15 13 package outline. . . . . . . . . . . . . . . . . . . . . . . . 16 14 revision history . . . . . . . . . . . . . . . . . . . . . . . 17 15 contact information . . . . . . . . . . . . . . . . . . . . 17 16 contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

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